The present invention relates to a vector processing apparatus which is composed of two processing units, i.e. a scalar processing unit and a vector processing unit.
A vector processing apparatus which includes two kinds of processing units, that is, a scalar processing unit and a vector processing unit which are designed to execute scalar instructions and vector instructions, respectively has been known. In conjunction with the execution of these two types of instructions, there are proposed and adopted at present two kinds of processing strategies.
According to the first processing strategy, a mixed series or chain of instructions including scalar instructions and vector instructions in a mixed sequence, is decoded by a decoder for controlling executions of the individual instructions. A typical example of such a strategy is system disclosed in an article by Richard M. Russell; "The CRAY-1 Computer System" contained in "Communications of the ACM", (Jan. 1978).
According to a second processing strategy two types of instructions, i.e. scalar instructions and vector instructions are decoded by using two respective proper decoders. A typical system using this strategy is discussed, for example, in T. Odaka et al's article "HITACHI SUPERCOMPUTER S-810 ARRAY PROCESSOR SYSTEM" contained in "SUPERCOMPUTERS" published by Elevier Science Publishers B.V. (North-Holland), 1986. In this system, instructions are decoded by two logical units.
The first system is characterized in that control over two species of instructions inclusive of the control for ensuring proper sequence established between the scalar instructions and the vector instructions can be realized in a facilitated manner by virtue of the fact that the scalar instructions and the vector instructions are present admixedly.
On the other hand, the second system allows the two types of instructions to be executed independent of each other to thereby facilitate the parallel processing because the scalar instruction processing or decoding unit is separated from the vector instruction processing unit. However, the independence of the scalar processing unit and the vector processing unit from each other means in turn that the vector processing unit has to be activated by the scalar processing unit. For activation of vector processing unit, all variety of information required for initiating the vector processing has to be set up by the scalar processing unit. This setting-up processing tends to involve an extended time for preparation before the vector computation is started, rendering it difficult or even impossible to make use of the functional performance specific to the vector processing unit for the computation of vectors of short vector length. Additionally, the second mentioned system requires means for informing the scalar processing unit of the fact that a given processing of significance has been completed on the part of the vector processing unit at a given time.
As will be understood from the above description, the second system can enjoy a greater degree of freedom over the first system because of the capability of parallel processing, and is more effective for realizing advanced parallel computation. However, in order to combine the advantages over the first system with the performance of the processing units of the second system, adequate consideration must be paid to the activation of the vector processing unit and the synchronous control of the scalar processing unit.